386/486/Pentium-specific Opcodes
Opcodes on this page are supported by 386+. Opcodes for 486+ and Pentium are
flagged.
Note: On 386+ computers, the "word size" can be 32 bits instead of 16
bits. This affects many opcopdes includng String Operations. In
real mode, 16-bit registers and address operands are the default.
In protected mode, the descriptor for CS indicates the default.
At any time you can use a SIZ or ADDRSIZ prefix to toggle from
the default to the other mode for the next operation.
SIZ (prefix; 66H) next data reference is non-default size
ADDRSIZ (prefix; 67H) next address reference is non-default size
BSF reg,src Bit Scan Forward. Put index of next 1-bit of src into reg
BSR reg,src Bit Scan Reverse. Put index of prev 1-bit of src into reg
(both: ZF is set and reg←0 if src contains all 0s)
BSWAP reg32 Swap low-to-high ordering of 4-byte reg32 to high-to-low
ordering. 486+
BT r/m,im8 Test bit. Put bit im8 (or reg) of reg/mem into CF.
r/m,reg (im8 or reg is used modulo 16 or modulo 32)
BTC r/m,im8 Test bit im8 (or reg) of r/m & complement that bit.
r/m,reg
BTR r/m,im8 Test bit im8 (or reg) of reg/mem and reset that bit.
r/m,reg
BTS r/m,im8 Test bit im8 (or reg) of reg/mem and set that bit.
r/m,reg
CMPXCHG r/m,reg Compare and Exchange. 486+
CMPXCHG8B Compare and Exchange 8 bytes Pentium
CPUID Get info into EBX,ECX,EBX (mode is 0 or 1 in EAX) Pentium
INVD Invalidate Data Cache. 486+
INVLPG mem Invalidate Translation Lookaside Buffer (TLB) entry 486+
JECXZ target Jump to target if ECX is 0.
LFS reg,mem Load FS and reg from memory.
LGS reg,mem Load GS and reg from memory.
LSS reg,mem Load SS and reg from memory.
MOV CRn,src32 Load src32 data into Control Register n (0,2,or 3)
MOV dest,CRn Load Control Register n into dest (reg/mem32)
MOV DRn,src32 Load src32 data into Debug Register n (0-3,6,or 7)
MOV dest,DRn Load Debug Register n into dest (reg/mem32)
MOV TRn,src32 Load src32 data into Test Register n (3-7)
MOV dest,TRn Load Test Register n into dest (reg/mem32)
SETccc dest If condition ccc is true, set the byte at dest to 1;
else, set it to 0. (ccc is the same as conditional
jump ops; see Execution Control Instructions)
RDMSR reg/mem Read from model-specific register in ECX Pentium
RDTSC Read timestamp counter (calculate clock cycles) Pentium
ROL/ROR/RCL/RCR/
SHL/SAL/SHR/
SAR r/m,im8 Shift/rotate by immediate count
im8 is forced mod 16 or mod 32 internally
SHLD r/m,reg,im8 Shift left r/m (16- or 32-bit) by im8 (or CL) bits,
SHLD r/m,reg,CL inserting data from reg into the vacated positions
SHRD r/m,reg,im8 Shift right r/m (16- or 32-bit) by im8 (or CL) bits,
SHRD r/m,reg,CL inserting data from reg into the vacated positions
WBINVD Write-Back and Invalidate Data Cache 486+
WRMSR reg/mem Write to model-specific register in ECX Pentium
XADD r/m,reg Exchange and Add 486+
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Instruction Set